找到你要的答案

Q:How long takes a multiplier function on FPGA? and is it possible to calculate this time?

Q:多久需要乘法器的功能在FPGA?是否有可能计算这个时间?

I have implemented a hardware architecture on FPGA and i use some multiplier function on this architecture ,

I'd like to know is there any way or method on ISE software or hardware (by using chip scope) to calculate the maximum delay time of each section/step?

for example i want to know if i increase the input clock pulse, which sections won't work correctly?

我对FPGA实施了硬件架构和我使用乘法器的功能,在这种体系结构,

我想知道的是在ISE软件或硬件的任何方式或方法(利用芯片范围)计算各部分/步最大延迟时间?

例如,我想知道,如果我增加输入时钟脉冲,哪些部分不能正常工作?

answer1: 回答1:

Look at the timing report for the design, which can give you delay information about various elements in a requested path.

Based on this you can also get minimum slack information, which then tells you how much you may increase the clock, and you can then change the clock frequency and rerun synthesis to check that it holds timing with the new clock frequency.

Using specific measurement, from for example chip scope, only gives information about that specific chip, on that specific power supply, with that specific data, etc., where the timing engine (Static Timing Analysis (STA)) given you a worst case analysis for design and vendor parameters.

查看设计的时序报告,它可以给您在请求路径中的各种元素的延迟信息。

在此基础上还可以得到最小松弛的信息,然后告诉你如何可以增加时钟,然后你可以改变时钟频率和运行综合检查,认为随着新的时钟频率定时。

使用特定的测量,例如芯片范围,只是给出了具体的芯片资料,在特定的电源,用具体的数据,等,其中时序引擎(静态时序分析(STA))给你一个最坏情况分析设计和供应商的参数。

fpga